A4 Conference proceedings

Calibration, bias and monitoring system for the VFAT3 ASIC of the CMS GEM detector

Publication Details

Authors: Licciulli F., Aspell P., Dabrowski M., De Lentdecker G., De Robertis G., Idzik M., Irshad A., Loddo F., Petrow H., Rosa J., Tuuva T.

Publication year: 2017

Language: English

Title of parent publication: 2017 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI)

Start page: 1

End page: 4

Number of pages: 4

ISBN: 978-1-5090-6708-4

eISBN: 978-1-5090-6707-7

JUFO level of this publication: 0

Digital Object Identifier (DOI): http://dx.doi.org/10.1109/IWASI.2017.7974222

Permanent website address: http://ieeexplore.ieee.org/document/7974222/

Open Access: Not an Open Access publication


VFAT3 is the last version of a family of multichannel trigger and
tracking ASICs designed for the upgrade of the CMS experiment in the
LHC. The chip has been developed to provide fast trigger information
from the readout of gas particle detectors improving the resolution of
the time measurement. The VFAT3 architecture comprises 128 analog
channels, each one composed by a low noise and low power charge
sensitive amplifier, shaper and constant fraction discriminator. The
comparator output is synchronized with the LHC clock and sent both to a
fixed latency path for trigger signal generation and to a variable
latency path for storage and readout. The front-end amplifier is
programmable in terms of gain and pulse shaping time, in order to adapt
it to a wide range of gaseous detectors as well as silicon detectors.
The chip also comprises a programmable calibration system that can
provide both voltage and current pulses. There are also two internal 10
bit ADCs for the monitoring of the internal bias references. The digital
logic provides trigger generation, digital data tagging and storage,
data formatting and data packet transmission with error protection on
320Mbps e-link. The digital design is triplicated in order to improve
the radiation hardness of the system. A first run of the chip of
9.1×6.1mm2 in 130nm technology node has been submitted and
produced. Chip architecture, measurements and characterization of the
calibration, bias and monitoring system will be shown.

Last updated on 2019-22-01 at 11:04