A4 Conference proceedings

VFAT3: A Trigger and Tracking Front-end ASIC for the Binary Readout of Gaseous and Silicon Sensors

Publication Details
Authors: Aspell Paul, Bravo Cameron, Dabrowski Mieczyslaw, De Lentdecker Gilles, De Robertis Giuseppe, Firlej Mirosław, Fiutowski Tomasz, Hakkarainen Tuomas, Idzik Marek, Irshad Aamir, Leroux Paul, Licciulli Fransesco, Loddo Flavio, Muhammad Ali, Moron Jakub, Petrow Henri, Świentek Krzysztof, Tavernier Filip, Tuuva Tuure
Publication year: 2019
Language: English
Title of parent publication: 2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC)
ISBN: 978-1-5386-8494-8
eISBN: 978-1-5386-8495-5
ISSN: 1082-3654
eISSN: 2577-0829
JUFO-Level of this publication: 1
Open Access: Not an Open Access publication


VFAT3 is the front-end ASIC designed specifically for the readout of GEM
detectors within the CMS experiment during the high luminosity phase of
the LHC at CERN. This paper presents the analog and digital design plus
the measured functional and characterization results. Key design goals
were optimization to GEM charge characteristics maximizing signal to
noise, timing resolution and operation at high particle rate. There are
128 front-end channels comprising preamplifier, shaper and constant
fraction discriminator (CFD). Features include programmable polarity
(for use with gaseous MPGD or silicon detectors), programmable gain (for
linearity 9.5 fC, 28 fC and 55 fC) and programmable shaping times (15
ns, 25 ns, 36 ns and 45 ns), plus the CFD reducing time walk to less
than 0.4 ns within 3 fC to 30 fC of input charge, optimizing timing
resolution. An internal calibration circuit allows calibration of each
channel with "GEM like" or "Silicon like" input pulses, each having
programmable amplitude, polarity and phase. The ENC measures 620 e + 33
e/pF in high gain. The hit rate capability is demonstrated to 2 MHz per
channel. VFAT3 has 2 output paths; the first (Trigger Path) provides hit
information for every LHC clock cycle. The second (Data Path) provides
data packets upon receipt of a trigger, each data packet contains hit
information and time stamps. The chip can operate with trigger latencies
up to 25.6 μs and is capable of receiving consecutive triggers. VFAT3
can operate with up to 2 MHz trigger rate in default mode and has data
packet zero suppression capabilities to go beyond this rate. An internal
dedicated Comm-Port allows communication to and from the chip.
Additional features include channel input protection, internal/external
temperature measurement and design for a radiation environment. The
design and measurements presented demonstrate the VFAT3 capability as a
complete binary front-end readout ASIC optimized for GEM detectors in
the high luminosity LHC.

Last updated on 2020-20-03 at 10:03